1. Field of the Invention
This invention relates to a nonvolatile memory system, and particularly to a floating gate type, Electrically Erasable and Programmable Read Only Memory system (hereinafter, EEPROM system) which can store multiple values in one memory cell thereof.
2. Brief Description of the Related Art
An example of a conventional, nonvolatile memory system for storing multiple values in its single memory cell is disclosed in Japanese Kokai Publication, No. 67997/80.
FIG. 1 is a circuit diagram of the memory cell of the conventional nonvolatile memory system described in the Japanese Kokai publication, No. 67997/80. As shown in FIG. 1, the memory cell comprises a first diode 16 and a second diode 20, which are easily caused to break down by supplying a reverse voltage, a first series of conventional diodes 18-1 to 18-n (n an integer greater than 1), and a second series of conventional diodes 22-1 to 22-m (m an integer greater than 1, m.noteq.n).
A cathode of the first diode 16 is connected to a first address line 10, and a cathode of the second diode 20 is connected to a second address line 12. Further, a cathode of the lead diode 18-1 of the first series of conventional diodes 18-1 to 18-n is connected to a selection line 14, and a cathode of the lead diode 22-1 of the second series of the conventional diodes 22-1 to 22-m is also connected to the selection line 14. An anode of the first diode 16 is connected to an anode of the last diode 18-n of the first series of the conventional diodes 18-1 to 18-n, and an anode of the second diode 20 is connected to an anode of the last diode 22-m of the second series of the conventional diodes 22-1 to 22-m.
In a writing process, there is provided a relatively high reverse potential between the selection line 14 and the first address line 10 and/or between the selection line 14 and the second address line 12. Thereby, the first diode 16 and/or the second diode 20 is caused to break down and loses its diode characteristic. In other words, the diode 16 and/or 20 becomes an ordinary conductor.
On the other hand, in a reading process, there is provided a reading potential on the selection line 14 and an outer circuit (not shown) senses a voltage differences between the selection line 14 and both of the first address line 10 and the second address line 12. If either the first diode 16 or the second diode 20 has broken down, a voltage difference will appear by means of the first series of diodes 18-1 to 18-n or the second series of diodes 22-1 to 22-m.
Therefore, there are provided three different values of the voltage difference according to the break down status of the cell.
In this way, there can be stored one of three "values" in the single memory cell, such as respective representing: (1) both of the diodes have broken down, (2) one of the diodes has broken down, or (3) neither of the diodes has broken down.
However, the above described circuit configuration has the following disadvantages:
(1) Once either of the first and second diodes 16 and 20 has broken down, this is a permanent condition so the memory cell cannot be rewritten. In other words, this circuit configuration is a destructive read only memory.
(2) Since the number of different values which a single memory cell can store is dependent on the number of the diodes in the memory cell, it is necessary to include a large number of diodes in the memory cell if it is desired that the cell can store a large number of different values.
(3) It is necessary to provide a relatively high power source (0.5-1.0 W) for a writing process to cause the break down of the first and second diodes 16 and 20. Therefore, it is difficult to write into the memory cell if the memory cell is already assembled with another complete circuit. Further, it is difficult to write a plurality of values simultaneously into an array of such cells with low power consumption.
Another example of a known nonvolatile memory system, in the form of an EEPROM system, is disclosed in Japanese Kokai publication 59693/89 published on Mar. 7, 1989 which corresponds to U.S. Pat. No. 4,907,202 issued Mar. 6, 1990.
FIG. 2 is a block diagram of the EEPROM system described in the Kokai Publication 59693/89. As shown in FIG. 2, this EEPROM system comprises a clock pulse generator 24, a pumping circuit 26, a regulator circuit 28, a rise control circuit 30, a pair of high voltage switching circuit 32 and 34, a memory cell, and a reading circuit 38.
In this example, the clock pulse generator 24 generates a clock signal .phi. whose frequency is approximately 5 to 10 MHz and whose potential is 5 volts. The clock signal .phi. is pumped to a relatively high voltage signal VPP of 20 to 25 volts by the pumping circuit 26.
The high voltage signal VPP is regulated to have a predetermined potential level by the regulator circuit 28 and smoothed by the rise control circuit 30 to have a relatively slow rising waveform, for example, 16 v/ms. An object to smooth the shape of the high voltage signal VPP is to prevent destruction of the memory cell and a writing error caused by a too sharply rising waveform.
The high voltage signal VPP after being regulated and rise controlled by circuits 28 and 30, is output as a high voltage writing pulse WR to the memory cell 36 by the high voltage switching circuit 32 during a writing operation which is activated by a write enable signal W. The high voltage signal VPP is also applied as a high voltage erasing pulse ER to the memory cell 36 by the high voltage switching circuit 34 during an erasing operation which is activated by an erase enable signal E.
The memory cell 36 includes a conventional floating gate tunnel oxide type transistor (hereinafter, FLOTOX transistor). During a writing operation, the FLOTOX transistor stores positive electric charges in its floating gate so that the threshold between its drain and source is changed. During an erasing operation, those positive electric charges are removed from the floating gate to again change the threshold. The reading circuit 38 is activated by a read data signal RD and detects such a change of threshold and outputs an output data signal Dout.
However, since a high voltage pulse applied to the memory cell 36 for a writing operation has a fixed level and a fixed duration and the reading circuit 38 detects only whether the threshold has changed or not, the memory cell 36 can store only two values, these being represented by whether the threshold is high ("H") or low ("L").